In the semiconductor industry, various processes can be used to deposit and remove conductive materials on the wafers. Deposition techniques include processes such as electrochemical deposition (ECD) and electrochemical mechanical deposition (ECMD). In both processes, a conductor such as copper is deposited on a semiconductor wafer or a workpiece from a process solution, such as an electrolyte, that comes into contact with the surface of the wafer and an electrode. Material removal techniques include chemical etching, electrochemical etching, electrochemical mechanical etching and chemical mechanical polishing.
The term of Electrochemical Mechanical Processing (ECMPR) is used to include both Electrochemical Mechanical Deposition (ECMD) processes as well as Electrochemical Mechanical Etching (ECME), which is also called Electrochemical Mechanical Polishing (ECMP). It should be noted that in general both ECMD and ECMP processes are referred to as electrochemical mechanical processing (ECMPR) since both involve electrochemical processes and mechanical action on the workpiece surface.
In one aspect of an ECMPR method, a workpiece-surface-influencing-device (WSID) such as a mask, pad or a sweeper is used during at least a portion of the electrotreatment process when there is physical contact or close proximity and relative motion between the workpiece surface and the WSID. Descriptions of various deposition and etching methods, including planar deposition and planar etching methods i.e. ECMPR approaches and apparatus, can be found in U.S. Pat. No. 6,176,952 entitled “Method and Apparatus For Electro Chemical Mechanical Deposition”, and U.S. Pat. No. 6,534,116 entitled “Plating Method and Apparatus that Creates a Differential Between Additive Disposed on a Top Surface and a Cavity Surface of a Workpiece Using an External Influence, both commonly owned by the assignee of the present invention.
Regardless of the deposition or removal process used, conventionally the workpiece is transferred to some type of cleaning and drying station after processing. During the cleaning steps, various residues generated by the processing are rinsed off the workpiece, and subsequently the workpiece is dried by spinning and if necessary blowing a gas such as nitrogen on its surface.
In one exemplary design, the processing chamber, in which conventional plating or removal processing or ECMPR occurs, and the rinse chamber can be stacked vertically in a vertical process chambers arrangement. In this arrangement, the processing can be performed in a lower chamber, and the cleaning and drying can be carried out in an upper chamber after isolating the upper chamber from the lower chamber so that chemicals used in either chamber do not mix with each other. One such vertical chamber is disclosed in U.S. Pat. No. 6,352,623 entitled “Vertically Configured Chamber Used for Multiple Processes”, commonly owned by the assignee of the present invention.
Conventional electroplating methods for depositing metals such as copper in damascene and non-damascene type structures typically produce a metal deposit with topographic profiles. FIG. 1 illustrates a cross-sectional view of a surface region of an exemplary workpiece 102 such as a semiconductor wafer with topographic features 104 such as trenches and vias formed into the insulating, or dielectric, layer 110 of the workpiece 102. In conventional deposition processes, a barrier layer 108, and then, in the case of copper deposition, a very thin copper, copper alloy or non-copper seed layer 112 are coated onto the insulating layer 110 and into the features 104.
Metal deposition onto the workpiece 102 having features such as features 104 generally produce a thick overburden or excess metal layer. The top surface of the overburden metal layer is usually conformal with the deepest and widest features. As shown in FIG. 2, copper is deposited onto the wafer 102 to form a copper layer 106. Typically, the goal of a planarization process is to remove the metal from the top surface of the wafer 102, leaving the metal only in the features 104. This is presently achieved by a polishing technique such as chemical mechanical polishing (CMP) as well as ECP or ECMP processes as referred to above, or a combination of these techniques.
With a patterned wafer 102 that has features 104, the copper when deposited onto the wafer 102 will tend to align to the features 104, leaving valleys 114 in a top surface 116 of the copper layer 106. In most commonly used CMP approaches, the surface of the workpiece 102 is contacted with a polishing pad and the pad is moved with respect to the surface. The role of the pad is to polish the surface of the workpiece 102 and to remove the copper on the surface with the help of, for example, a chemical solution or slurry containing abrasive particles. When CMP techniques are used to remove a portion of the metal layer, resulting in the planarized workpiece 102 shown in FIG. 3, the dielectric layer 110 of the workpiece 102 receives uneven pressure from a polishing tool due to the valleys 114 in the copper layer 106 in FIG. 2. Further, the force from the CMP polishing pressures can locally exceed the fracture strength of the dielectric, or any of the metal-dielectric interfaces. This, in turn, may result in defects such as cracks in the dielectric layer or delamination at the interfaces of dissimilar materials such as interfaces of dielectric and copper or barrier layer and dielectric layer, etc. Such defects lowers the overall process yield and productivity. For this reason, fragile insulators and many low-k films forming the dielectric layer 110 are easily damaged during CMP operations on metals 106 such as copper.
This damage can be seen as cracks 118 in the dielectric layer as exemplified in FIG. 4 that shows the cross-section of the same workpiece 102 after, for example, a CMP technique has been applied beyond the planarization achieved in FIG. 3. As the excess copper and the barrier layer 108 outside the features are removed in order to fully isolate the structures of interest, the dielectric layer 110 of the workpiece 102 is damaged and defects such as cracks 118 are formed.
FIG. 5 illustrates an exemplary workpiece 152 having a very deep trench 166a and a via 166b into the dielectric layer 160 over the barrier layer 158 and the seed layer 162. In deep to very deep trench plating applications, the depth of the features 166 of interest may range from 3 to 100 microns, while the width of the features 166a,166b may range from below 1.5 micron to above 100 microns. In FIG. 5, the depth of the trench 166a is approximately 30 microns, while the widths of the trench 166a and the via 166b are approximately 200 microns and 10 microns, respectively. Of course, these exemplary dimensions of FIGS. 5 and 6 are presented for purposes of illustration, and the application of FIGS. 5 and 6 to other dimensions will be readily understandable to one skilled in the art.
The exemplary workpiece 152 presents a unique difficulty for conventional damascene plating processes. For example, performing conventional damascene plating on the 30 micron deep trench 166a would result not only in very long plating times, but the CMP process to polish over 30 microns of a copper layer 156 would be very expensive. For instance, a 30 micron deep feature may require about 500 nm seed layer 162. Typically, about 35 microns of plate copper would be needed to deposit on the workpiece 152, as shown in FIG. 6. The removal of this large overburden layer 156 by CMP process, or by other methods, will be quite expensive.
Avoiding damage to fragile dielectric films on workpieces and substrates presents a challenge for state of the art CMP techniques. The higher the polishing pressure, the higher the metal removal rates are during CMP operations. Higher polishing pressures, while practical for strong dielectric films, are problematic for many films with low dielectric constants, let alone porous dielectrics. This is because these films tend to be more fragile than, for example, silicon dioxide. In general, CMP operations that occur at low pressures do minimize the damage to fragile dielectrics, but the operations result in lower metal removal rates, hence lower process throughput and higher operating costs.
The ECMD and ECMP techniques referred to above, or a combination thereof, are often successful in obtaining a planar conductive surface over what had previously been a non-planar conductive layer, as described, for example above mentioned in U.S. Pat. No. 6,176,992. While usage of an ECMD process or an ECMD/ECMP process is advantageous, having other techniques that can assist or supplement these and other processes to provide planarization is desirable.
In addition to the challenges posed by metal overburden on workpieces having topographical features, when a metal such as copper is plated on a wafer front surface, in addition to areas on the front surface where there are ICs, the copper may also deposit on the edges and sides, i.e., bevel, of the wafer where no ICs or circuits are located. In some cases, the edge and bevel are protected from the plating solution; therefore no copper may be plated there. However, there may still be a copper seed layer on the edge regions and bevel. Whatever the source is, such remaining copper, i.e. the edge copper, may migrate to neighboring active regions from the sides and edges of the wafer, especially during an annealing step. Further, copper particles originating from a wafer edge may contaminate the wafer transport system, and other process equipment such as the annealing system etc., and so be passed on to contaminate other wafers. Poorly adhering copper flakes from the wafer edge may also cause problem during the CMP step by becoming loose and getting onto the surface areas where there are circuits. For these reasons and more, it is important to remove the copper from the edges and the bevel of the wafer following each copper plating process step.
Thus, there is a need in the semiconductor industry for systems and processes that allow for more efficient processing, including further techniques to planarize workpiece surfaces and to provide more precise control of deposition and removal processes while preserving the structural integrity of the dielectric layer and reducing operational costs, and to assist with the removal of, and to inhibit formation of, excess copper from the edges and bevel of a workpiece such as a semiconductor wafer.